Fault location in Reed-Muller canonic networks
K.L. Kodandapani · Proceedings of the Institution of Electrical Engineers · 1977
In the paper, single and multiple-fault locating test sets for Reed-Muller canonic networks are derived. The fault model assumes stuck-at faults at the I/O leads of AND gates, and that an EOR gate under a fault can produce any other function of two inputs other than equivalence. The results in the paper give an insight into the complexity of testing of a class of logic networks.