Verification of asynchronous logic circuit design using process algebra
Tomohiro Yoneda, Atsufumi Shibayama, Takashi Nanya · Systems and Computers in Japan · 1997
Asynchronous circuits are attracting attention because they can provide solutions to clock-skew and power dissipation problems of synchronous circuits. On the other hand, asynchronous circuits are more complex than synchronous circuits, and so formal verification becomes an essential step in the asynchronous circuit design. In this paper, we propose an approach to the formal verification of asynchronous circuits based on process algebra. In our approach, we describe both the asynchronous circuit and its specification using process expressions, and check the correctness of the circuit with respect to the specification by constructing the parallel composition of those processes. The advantages of this approach are that the descriptions are easily readable and that the method is fully automatic. Further, we propose a simple algorithm to check the restricted liveness properties of circuits. © 1997 Scripta Technica, Inc. Syst Comp Jpn, 28(8): 33–43, 1997