A Low-Power Architecture for the Design of a One-Dimensional Median Filter
Ren-Der Chen, Pei‐Yin Chen, Chun-Hsien Yeh · IEEE Transactions on Circuits & Systems II Express Briefs · 2014
This brief presents a low-power architecture for the design of a one-dimension median filter. It is a word-level two-stage pipelined filter, receiving an input sample and generating a median output at each machine cycle. The power consumption is reduced by decreasing the number of signal transitions in the circuit. This can be done by keeping the stored samples immobile in the window through the use of a token ring in our architecture. The experimental results have shown that, at the expense of some additional area cost, the power consumption can be successfully reduced.