VHDL implementation of an optimized 8-point FFT/IFFT processor in pipeline architecture for OFDM systems
Mounir Arioua, Saïd Belkouch, Mohamed Agdad, Moha M’Rabet Hassani · 2011
The Fast Fourier Transform (FFT) and its inverse transform (IFFT) processor are key components in many communication systems. An optimized implementation of the 8-point FFT processor with radix-2 algorithm in R2MDC architecture is presented in this paper. The butterfly - Processing Element (PE) used in the 8-FFT processor reduces the multiplicative complexity by using a real constant multiplication in one method and eliminates the multiplicative complexity by using add and shift operations in other proposed method. The pipeline architecture R2MDC has been implemented with the 8-point module and simulation results show that this module significantly achieves a better performance with lower resource usage.