Test Engineering for CMOS Gate Arrays with the CAD-System VENUS 1
Olaf Scherer · IEEE Transactions on Industrial Electronics · 1986
This paper describes the application of the computer-aided design/computer-aided testing (CAD/CAT) system VENUS 1 at Siemens for testing CMOS gate arrays [1]. The requirements for and the industrial aspects of CMOS gate array testing will be discussed.