IP design for DIF, integrated in Nios II systems
Trifon Trifonov · 2014
The paper discusses the main results of hardware implementation of digital image filters (DIF) on Field Programmable Gate Arrays (FPGA). It defines the system architecture, the IP architecture and the averaging filter implementation's specifics. It has been made a comparative analysis with variety of test scenarios and configuration of software implementation of DIF on Nios II embedded processor against the proposed hardware implementation. It's been investigated the maximum operating frequencies of the proposed architecture and how much is accelerated computational process. As a result, the DIF IP is implemented with VHDL, integrated in Altera's Qsys Component Library and verified on Altera Cyclone IV FPGA device.