A SIMULATION STUDY ON THE INTERACTIONS BETWEEN MULTITHREADED ARCHITECTURES AND THE CACHE
Weng‐Fai Wong, Eiichi Goto · International Journal of High Speed Computing · 1994
As processors’ speeds increase, the problems of the memory and communication bottlenecks have resurfaced. Recently, there have been growing interest in the design of multithreaded architecture which can potentially overcome these problems. In such architectures, hardware is used to maintain a fixed number of instruction streams out of which instructions may be issued. The motivation of this study is to examine the effects of such architectures on the cache, which so far has been the mainstay against the memory bottleneck problem. Unlike previous studies of caches in multiprogramming systems, multithreaded architectures switch contexts much more rapidly. We will present and analyze results on the effects of the number of streams and the stream switch interval on the cache. Our results show significant differences from those previously obtained from multiprogramming experiments. We have also studied the interaction of the various cache parameters (cache size and associativity, in particular) with these two new parameters. Our findings confirm the intuition that multithreading will lead to a higher cache miss ratio. However, our findings give a more detailed picture of the interactions involved.