Real-time interconnection network for single-chip many-core computers
Harald Richter · 2013
A real-time capable interconnection network for single chip many-core computers is presented that is superior to the known Benes network because its routing algorithm scales linearly with the number of switches, and because it has a modular setup which eases chip synthesis and test. Its routing is based on “separation and approximation”. This method can also be applied to the Benes network, thus making its looping routing obsolete.