Novel low-power 12-bit SAR ADC for RFID tags
Daniela De Venuto, Eduard Stikvoort, David Tio Castro, Youri V. Ponomarev · 2010
A novel design and measuring results of an ultra-low power 12bit Successive-Approximation ADC for autonomous multi-sensor systems are presented. The comparator and the DAC are optimised for the lowest power consumption. The proposed design has a power consumption of 0.52¿W at a bitclock of 50-kHz and of 0.85¿W at 100-kHz with a 1.2-V supply. The Figure-of-Merit reached with such implementation is of 66 fJ/conversion-step. The ADC was realised in the NXP CMOS 0.14¿m technology with an area of 0.35 mm2. Only four metal layers were used in order to allow 3D integration of the sensors.