Improvement of the majority gate algorithm for greyscale dilation/erosion
Antonios C. Gasteratos, Ioannis Th. Andreadis, P. Tsalides · Electronics Letters · 1996
An improvement of the majority gate algorithm suitable for grey scale morphological operations is presented in the Letter. The redundancy of temporal signals led to a simplified hardware implementation. It is shown that max/min operators can be computed by the same circuit. A new pipelined systolic array architecture based on this circuit is illustrated for dilation/erosion operations.