Low-power video decoding system using a reconfigurable processor
Joon Ho Song, Won Chang Lee, Doo Hyun Kim, Do-Hyung Kim, Shihwa Lee · 2012
A reconfigurable processor based video decoding system with bistream decoding instruction and memory processing co-processor is presented. Experimental results show that the performance is enhanced about 42% than processor only system. We also estimate that the power consumption is lower than the hardware system about 24% at SD resolution.