Estimating variation in IC yield estimates
Virginia Foard Flack · IEEE Journal of Solid-State Circuits · 1986
Many methods have been proposed for obtaining IC yield estimates as IC areas increase. These estimates are by their very nature variable. The variability of the proposed yield estimates has not yet been discussed in the literature. The author describes a method for deriving formulas for the variance and standard deviation of yield estimates, using Stapper's negative binomial model as a detailed example. Computations based on Moore's half-slice data give standard deviations near 3.0% for different die areas.