Reducing Test Time of Power Constrained Test by Optimal Selection of Supply Voltage
Praveen Venkataramani, Vishwani D. Agrawal · 2013
As supply voltage is reduced, a power constrained test clock can be sped up in spite of the increased delay of the circuit. However, a large reduction in voltage makes the operation structurally constrained, requiring the clock to slow down. We determine an optimum supply voltage that allows fastest clock speed for a given power limit. Examples show that the test time can be reduced by as much as 63% from the nominal voltage test time. In a typical application, this technique can reduce the cost of wafer sort.