Design of Low-Offset Voltage Dynamic Latched Comparator
Mayank Nema · IOSR Journal of Engineering · 2012
The offset voltage of the dynamic latched comparator is analyzed in detailed and dynamic latched comparator design is optimized for the minimal offset-voltage based on the analysis in this paper.As a result offset-voltage was reduced from 0.87µV (in conventional double tail latched comparator) to 0.3µV (in case of proposed comparator.The simulated results of the conventional as well as proposed comparator have been shown on pspice orcad 9.2 versions.