A decimal squarer with efficient partial product generation
Kuan Jen Lin, Yu Chan Chiu, Tzu-Hao Lin · 2010
Hardware realization of decimal arithmetic operations is becoming a necessity in commercial, financial and internet-based applications. Exponentiation is a frequently used but time-consuming operation for these applications. Usually, squaring and multiplication are combinedly used to simplify exponentiation. Though research in decimal multiplication has received a lot of attention, the exploration of dedicated hardware design for decimal squaring so far is lacked. This work uses digit-squarers rather than digit-multiplier as core circuits to generate all partial products. Circuit area and delay both are significantly reduced. A 7-digit decimal squarer was implemented with an iterative structure. Compared to digit-multiplier based multipliers, the proposed design achieves up to 44% reduction of the area-time product.