CASTLE: an emulated digital CNN architecture design issues, new results
Ákos Zarándy, Peter Keresztes, T. Roska, P. Szolgay · 2002
A new emulated digital CNN universal machine chip architecture is introduced in this paper. The chip contains 24 CNN core processors using 70 mm/sup 2/ silicon area with a 0.35 /spl mu/m technology. Its speed is 1 ns/virtual cells/CNN iterations with 12 bit precision. This enables one to execute over five hundred 3/spl times/3 convolutions on each frame of a 240/spl times/320 sized 25 fps (standard NTSC) digital image flow. Another new feature of the design is the different precision capability. This allows the user to convert precision to speed.