On the topographic equivalence between voltage mode and current mode ranked order filters for array processors
Jussi H. Poikonen, A. Paasio · 2006
This paper examines the circuit implementation of programmable parallel analog order statistic filtering and compares the topographies of two compact ranked order filter circuit structures, which have been proposed for use in a CNN-type array processor, either for current or voltage mode inputs. The performance and complexity of the circuits is examined with respect to their practical implementability in a massively parallel architecture