A single-chip RSA processor implemented in a 0.5 μm rule gate array
S. Ishii, Kazuhiro Ohyama, Kiyoshi Yamanaka · 2002
A prototype single-chip modular exponentiation LSI is implemented, which is capable of high-speed RSA public-key encryption processing, in a 0.5 /spl mu/m-rule gate array. With this LSI, computation can be done using key arbitrary lengths of up to 1024 bits, and a throughput of 10 kbps can be achieved. This paper describes the technical aspects of the LSI's design and performance.>