A floating point convolution system
J.F. Panisset, J. Drolet, J.F. Cote, F. Larochelle, Alfred S. Malowany · 2002
The design of a double precision floating point convolution processor for the VMEbus is presented. It is based on a custom VLSI systolic cell as well as off-the-shelf and programmable ASIC devices. The architecture and design of the systolic cell and of the convolver card are presented, with particular emphasis given to the DMA interface to the VMEbus and the conversion of generated results from floating point to integer format.>