An architectural extension to the media core processor for HDTV applications
K. Yoshioka, H. Oka, H. Nishida, R. Matsuura, Tokuzo Kiyohara · Asia Pacific Conference on Circuits and Systems · 2003
Introduces an architectural extension to the media core processor (MCP), which targets a system solution for consumer multimedia products. This extension implements HDTV video decoding (1080i, 720p, 480p and 480i), video resizing, 2-D graphics rendering, and conversion between various video formats for data broadcasting. For pixel-level operations in HDTV applications, a SIMD-style processor has been introduced. However, image resizing causes a difference in data structure between source and result dynamically. Therefore, an advanced inter-PE (processing element) communication mechanism is necessary as an extension to the common SIMD-style architecture. This processor achieves the flexibility of pixel-level operation and the efficiency of high bandwidth. Adopting this new MCP architecture enabled us to improve image quality to fulfill the requirements for consumer products.