Partial Scan Design Based on Levelized Combinational Structure
Sungju Park · Journal of Electrical Engineering and Information Science · 1997
To overcome the large hardware overhead attendant in the full scan design, the concept of partial scan design has emerged with the virtue of less area and testability close to full scan. Combinational Structure has been developed to avoid the use of sequential test generator. But the patterns shifted on scan register have to be held for sequential depth period upon the aid of the dedicated HOLD circuit. In this paper, a new levelized structure is introduced aiming to exclude the need of extra HOLD circuit. The time to stimulate each scan latch is uniquely determined on this structure, hence each test pattern can be applied by scan shifting and then pulsing a system clock like the full scan but with much less scan flip-flops. Experimental results show that some sequential circuits are levelized by just scanning self-loop flip-flops.