Efficient test vectors for ISCAS sequential benchmark circuits
S.Y. Lee, Kewal K. Saluja · 1993 IEEE International Symposium on Circuits and Systems · 2002
The sequential automatic test pattern generation system FASTEST is implemented with new heuristics to produce efficient test vectors for sequential circuits. The efficiency of FASTEST in terms of the quality of test vectors is demonstrated. The test vectors provide excellent fault coverage by fairly short test sequences. The profile of the ISCAS benchmark circuits is also described.>