Interconnect-limited VLSI architecture
William J. Dally · 2003
As semiconductor technology scales, wires are becoming the dominant factor in determining system performance and power dissipation. By 2008, it is expected that chip traversal will require 16 clocks. Modern superscalar architectures that depend on global register files, global bypass structures, and global instruction issue logic are poorly matched to future semiconductor technology. This technology demands architectures that exploit locality and minimize global communication. In this paper, we describe three approaches to developing architectures that are well matched to interconnect-limited technology. These architectures reduce the use of global communication by clustering execution resources with their data and instruction storage and extending the storage hierarchy to the level of individual ALUs. They also make more efficient use of global interconnection by organizing it as a regular network, rather than a collection of ad-hoc dedicated wires.