A two-stage charge-based analog/digital neuron circuit with adjustable weights
Alexandre Schmid, Yusuf Leblebici, D. Mlynek · 2003
A circuit-level neuron architecture based on the principle of analog charge-based computation of neural functions has been developed with the goals of high-speed processing, adjustable weights, and support of perturbation-based learning algorithms. The two-stage architecture which is composed of nonlinear synapses, driving a linear capacitive soma, has been implemented using a conventional double-polysilicon CMOS technology. The feedforward architecture of the proposed neuron model is shown to synthesize a large number of nonlinear mappings of the 2D-1D space.