Thermal Issues in Testing of Advanced Systems on Chip
Nima Aghaee Ghaleshahi · Linköping University Electronic Press eBooks · 2015
Many cutting-edge computer and electronic products are powered by advanced Systems-on-Chip (SoC).Advanced SoCs encompass superb performance together with large number of functions.This is achieved by efficient integration of huge number of transistors.Such very large scale integration is enabled by a core-based design paradigm as well as deepsubmicron and 3D-stacked-IC technologies.These technologies are susceptible to reliability and testing complications caused by thermal issues.Three crucial thermal issues related to temperature variations, temperature gradients, and temperature cycling are addressed in this thesis.Existing test scheduling techniques rely on temperature simulations to generate schedules that meet thermal constraints such as overheating prevention.The difference between the simulated temperatures and the actual temperatures is called temperature error.This error, for past technologies, is negligible.However, advanced SoCs experience large errors due to large process variations.Such large errors have costly consequences, such as overheating, and must be taken care of.This thesis presents an adaptive approach to generate test schedules that handle such temperature errors.Advanced SoCs manufactured as 3D-stacked-ICs experience large temperature gradients.Temperature gradients accelerate certain early-life defect mechanisms.These mechanisms can be accelerated using gradientbased, burn-in like operations so that the defects are detected before shipping.Moreover, temperature gradients exacerbate some delay-related defects.In order to detect such defects, testing must be performed when appropriate temperature-gradients are enforced.Schedule-based techniques that enforces the temperature-gradients for burn-in like operations and delay testing are proposed in this thesis.