On-line detection of environmentally-induced delay faults in CMOS wave pipelined circuits
A. Martinez-Smith, Rishika Iytha Sridhar · 2002
Circuits designed with CMOS wave pipelined logic gates are not fully reliable, even after careful design and tuning, due to environmentally-induced faults. These faults are responsible for random propagation delays along certain paths. This paper addresses the need for on-line correction of these faults. It presents a delay fault sensing technique for CMOS wave pipelining and the results for a design style.