An incremental approach for test scheduling and synthesis using genetic algorithms
HAIDAR M. HARMANANI, A. Hajar · The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004. · 2004
This paper presents a new and an efficient method for concurrent BIST synthesis and test scheduling. This method maximizes concurrent testing of modules while performing the allocation of functional units, test registers, and multiplexers. The method is based on a genetic algorithm that efficiently explores the testable design space. The method was implemented using C++ on a Linux workstation. Several benchmark examples have been implemented and favorable results are reported.