A 90 nm 6.5 GHz 256×64 b dual supply register file with split decoder scheme
Steven Hsu, Bhaskar Chatterjee, Manoj Sachdev, Atila Alvandpour, Ram Kumar Krishnamurthy, Shekhar Y. Borkar · 2004
This paper describes a 256/spl times/64 b 2-read, 1-write ported static register file for 6.5 GHz operation in 1.2 V, 90 nm CMOS. Read/write select drivers and decoder use 0.9 V lower supply to reduce total energy by 23%. Local/global bitlines use a leakage-tolerant split-decoder scheme with conditional precharge to achieve 65% (90%) higher DC robustness compared to conventional static (dynamic) bitline scheme.