A 16 bit low-power-consumption digital signal processor for portable terminals
T. Ishikawa, Hajime Suzuki, H. Taki, Koichi Homma, Hideyuki Kabuo, M. Okamoto, K. Ueda, R. Asahi · 2002
This paper describes a 16-bit fixed point digital signal processor (DSP), which is targeted for telecommunication applications such as modems or low-bit-rate speech CODECs. A variable pipeline multiplier-accumulator (MAC) unit and several additional circuits such as a dual-purpose shift register are used to improve performance per MIPS. The DSP chip is fabricated with 0.5 /spl mu/m CMOS process and achieves 40 MIPS and 80 MOPS-peak performance at 3.0 V. A PSI-CELP (pitch synchronous innovation code excited linear prediction) speech CODEC can be implemented on this DSP with enough margin.