Communication architecture of EtherCAT master for high-speed and IT-enabled real-time systems
Tatsuya Maruyama, Tsutomu Yamada · 2015
We propose a communication architecture for EtherCAT master motivated by the technological progress in IT systems and Industrial Ethernet in control systems. In the proposed method, a dedicated hardware named the EtherCAT accelerator offers virtualized real-time and IT communication channels by operating automatic control frame generation, time synchronization protocol, and transmission scheduling of frames based on synchronized time. Using the EtherCAT accelerator enables highly accurate cyclic communications under IT communications such as IP. We prototyped the proposed architecture on a field programmable gate array (FGPA) as hardware and Linux as software. The results show that the master can transmit 64-byte packets in a 30 μs cycle synchronized to an EtherCAT network with less than 1 μs accuracy.