Implementing and Evaluating Stream Applications on the Dynamically Reconfigurable Processor
N. Suzuki, S. Kurotaki, Motohiro Suzuki, Naoto Kaneko, Yutaka YAMADA, K. Deguchi, Yohei Hasegawa, Hisayuki Amano, Kenichiro Anjo, Masato Motomura, Katsunori Wakabayashi, Takeshi TOI, Toru Awashima · 2004
Dynamically reconfigurable processor (DRP) developed by NEC electronics is a coarse grain reconfigurable processor that selects a data path from the on-chip repository of sixteen circuit configurations, or contexts, to implement different logic on one single DRP chip. Several stream applications have been implemented on DRP-1, the first prototype chip, and evaluation results are presented. By computing parallelly using the processing elements(PEs) and distributed memory modules, DRP-1 outperformed pentium III/4 and embedded CPU MIPS64 in some stream application examples. We also present programming techniques applicable on reconfigurable processors and discuss their feasibility in boosting system performance.