A universal BIST methodology for interconnects
Chi‐Yuan Chang, Chengwei Su · 1993 IEEE International Symposium on Circuits and Systems · 2002
A methodology for the design and implementation of an universal interconnect built-in self test module for boundary-scan-based interconnects is proposed. Such a methodology is able to test any interconnects without knowing their connection configuration in advance. The fault-free responses of different I/O ports under the selected walking sequence of ones are studied. The faulty syndromes are enumerated for different faults, and compared with the fault-free ones. Two verification criteria are derived to verify the correctness of the nets. A universal interconnect (UI)-BIST hardware is designed, implemented, and tested.>