Formal verification of digital circuits by 3-valued simulation
Ayman M. Wahba, E.J. Aas · 2002
A new technique for digital circuit verification is presented. The new technique is based on the 3-value simulator, 3 VS. Our motivation for utilizing 3 VS is the desire to bridge the gap between common industrial practice of verification through simulation, and the world of formal verification. A metric for verification coverage is defined, and it is shown to provide a lower bound of design confidence. 3 VS and OBDD-based formal verification are compared, and none of the methods is declared generally superior.