RAPTOR: a single chip multiprocessor
Sangwon Lee, Yun-Seob Song, Soo-Won Kim, Hyeong-Cheol Oh, Woo-Jang Hahn · AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) · 2003
A microarchitecture of a processor named RAPTOR is described. RAPTOR is a single chip multiprocessor developed for exploiting thread-level parallelism. RAPTOR includes four identical processors, a graphics coprocessor, and an external cache controller. Each processor has a 16 KB primary cache and implements SPARC version 9 instruction set architecture. The external cache controller provides direct connection to a large external second level cache. RAPTOR is designed as a building block of multiprocessor systems such as symmetric multiprocessor machines.