High-performance VLSI processor for robot inverse dynamics computation
Somchai Kittichaikoonkit, Michitaka Kameyama, T. Higuchi · 2002
A VLSI-oriented matrix multiply-addition processor (MMP) is proposed for minimum-delay-time inverse dynamics computation on a linear array structure. It is shown that the delay time of the inverse dynamics computation becomes minimum based on the concept of the odd-even alternative computation. The MMP architecture is systematically designed by using two types of data-dependence graphs of the odd-even alternative computation. It is demonstrated by the layout evaluation that the MMP can be easily implemented in a single chip using the current VLSI technology (e.g. 1 mu m CMOS). The performance with regard to the delay time is higher than for previously reported architectures.>