Implementation of a 6.5 MHz 34-B NCO [numerically controlled oscillator]
Shi Yunhua, Sheng Shimin, Yue Liu, Ji Lijiu · 2002
An numerically controlled oscillator chip, using a pipelined structure, has been developed in standard 2 /spl mu/m P-well CMOS technology. The typical maximum input clock rate is 6.5 MHz. By analysis, the speed limiting factors improved are the delay of the accumulator and the data acquiring rate of the ROM. Through the use of an improved pipelined structure and N-well CMOS technology, an NCO device with a clock rate in excess of 10 MHz is indeed possible.