A new BIST architecture: design and implementation in VLSI
Xiaowen Sun, M. Olson, D. Yeung · 2002
The paper describes a new built-in self-test (BIST) scheme for combinational circuitry. It employs signature analysis and Berger code for off-line BIST, and parity code for concurrent checking, with common testing circuitry. The logic design and VLSI implementation of the proposed scheme for a ROM is presented. The hardware cost and performance characteristics of the designed chip are discussed. The error detectability of the scheme is evaluated.