CMOS implementation of a Viterbi detector for hard disk drives
P.A. Ziperovich, Jack K. Wolf · 2002
A PRML (partial-response maximum-likelihood) detector was implemented by interleaving two 1-D Viterbi detector ICs built using 1.2-/spl mu/m CMOS technology. The IC was designed to provide soft decision information output that can be used to extract system reliability information. The IC has real-time self-test capability using an internally generated pseudorandom binary sequence that provides test samples as if they were received through a noiseless 1-D channel. Fifty ICs were manufactured through the MOSIS service. The 1-D detector ICs were tested on the bench using the self-test feature, achieving a maximum speed of 40 Mb/s. A PRML board was built to test digital magnetic recording systems in the laboratory. The board performance was measured on the bench using simulated waveforms and additive white Gaussian noise. The PRML detector board is capable of achieving bit rates exceeding 50 Mb/s. The board was also tested with real heads and disks on a precision test stand.