A high speed, low power spread spectrum code generator
Menahem Lowy, K. Anne · 2002
This paper describes a parallel architecture implementation of a Gold code generator for a spread-spectrum communication system and its associated switch minimization algorithm. The parallel architecture dissipates less power than the conventional architecture based on serial linear feedback shift registers (LFSR) and also allows a higher throughput rate compared to the serial one where only one bit is generated per clock cycle. The Gold code generator implemented in a 2 micron CMOS technology consumes less than 1000 microwatts when clocked at 50 MHz.