A flexible high performance 2-D discrete cosine transform IC
L. Matterne, Dahae Chong, Brian McSweeney, R. Woudsma · 2003
The authors present an ASIC that is able to execute a two-dimensional discrete cosine transform (2D-DCT) algorithm and its inverse (2D-IDCT) at a maximum input sample rate of 13.5 MHz. It is demonstrated that a separable, orthogonal transform like the 2D-DCT can efficiently be mapped on a very long instruction word multiprocessor architecture, which may accommodate other algorithms. Some details and the test strategy are also elaborated.>