High performance DSP ASIC for multiply, divide and square root
Roger Woods, S.E. McQuillan, J. Dowling, John V McCanny · 2003
The design of a high-speed ASIC that combines the operations of multiplication, division and square root is described. The chip is based on a systolic array architecture that uses a redundant number system and allows multiplication, division, and square root to be combined on the same hardware. The chip has been designed using a 1.5- mu m, double-metal CMOS technology, operates on 16-b sign magnitude data, and has a throughput rate of 40 Msample/s for each operation.>