Multilevel timing-constrained full-chip routing in hierarchical quad-grid model
Jin-Tai Yan, Yen-Hsiang Chen, Chia-Fang Lee, Ming-Ching Huang · 2006
In this paper, given a set of timing-driven routing trees for all the interconnection nets, a new multilevel timing-constrained full-chip routing (MTFR) in a dynamic hierarchical quad-grid model is proposed to complete full-chip routing in reasonable time. The experimental results show that the proposed MTFR approach uses less CPU time to obtain 100% timing-constrained routing results for all the tested benchmark circuits.