A pipelined, high-precision FFT architecture
T. M. Hopkinson, G.M. Butler · 2003
Presents a highly integrated, high-precision fast Fourier transform (FFT) architecture. A 1.2- mu m CMOS implementation of this architecture has yielded a 32-b, 64K-point FFT that operates at a continuous four-million-samples-per second data rate. All FFT support functions, including coefficient generation and memory interfacing, are included on-chip. The heart of this architecture is a monolithic radix-4 FFT processor implemented as a full-custom VLSI circuit.>