Harvest model of an integrated hierarchical-bus architecture
R. Kermouche, Yvon Savaria, D. Audet · 2002
This paper presents a new approach to model the yield of a fault-tolerant hierarchical-bus structure, based on the expected value of the number of functional processors. With this method, easily computable mathematical expressions were obtained. Also, a defect tolerant communication network structure is proposed and analyzed in terms of additional hardware cost versus spares allocation. Assuming the network was successfully repaired, global reconfiguration of defective processing modules is then supported. Otherwise some graceful degradation would result. The results obtained, in terms of optimal distribution of spares in the communication network, show that complete duplication is not cost effective. However, redundancy can be added to the uppermost levels of the hierarchical tree in a very effective manner. Two harvest formulas were obtained; the first is an easily computed lower bound, and the second is exact according to the assumed defect density.>