Dynamic deficit round-robin scheduler for 5-Tb/s switch using wavelength routing
K. Yamakoshi, Eiji Oki, Naoaki Yamanaka · 2003
A dynamic deficit round-robin (DDRR) scheduling scheme for a 5-Tb/s switch is proposed. DDRR is a DRR-based packet scheduler and it can satisfy the max-min fair share. However, DRR cannot satisfy both high throughput and delay requirements. DDRR resolves the problem by changing the granularity for deficit counters according to the packet lengths at queue heads. Simulation results showing the efficiency of DDRR are presented and an implementation of DDRR for the switch is also described.