A new VLSI architecture of a hierarchical motion estimator for low bit-rate video coding
Jaehun Lee, Sung Deuk Kim, Sung Kyu Jang, Jong Beom Ra · 1999
We propose a new hierarchical motion estimator architecture that supports the advanced prediction mode of recent low bit-rate video coders such as H.263 and MPEG-4. In the proposed VLSI architecture, a basic searching unit (BSU) is commonly utilized for all hierarchical levels to make a systematic and small sized motion estimator. Also, since the memory bank of the proposed architecture provides a scheduled data flow for calculating the 8×8 block-based sum of absolute difference (SAD), both a macroblock-based motion vector (MV) and four block-based MVs per macroblock can be simultaneously obtained for the advanced prediction mode. Even with its small size of implementation, the proposed motion estimator provides similar coding performance as that of the full search block matching algorithm (FSBMA).