Logic simulation with interval-labelled net model
P.P.K. Chiu, Ying Shan Cheung · 2003
A novel approach to the application of an interval-labeled net model in logic simulation with timing among concurrent processes is introduced. By means of the model, logic circuit properties involving timing information can be specified and simulated in a multiprocessor-based environment using the token-passing algorithm. A logic simulator with timing information with a structure based on this approach is proposed.>