An efficient hardware architecture implementing wave digital filters with reduced wordlength coefficients
S. Summerfield, T. Wicks · 1992
Discusses the design and implementation of a wave digital filter architecture using coefficients that are taken from a restricted range. It outlines the possible advantages of this approach, with comparison to traditional complete coefficient ranges. Estimates of hardware speed in a VLSI implementation are made with reference to the ES2 1.5-micron process. >