Multiport memory and floating point Cordic pipeline in Jacobium processing elements
A. Looye, Gerben J. Hekstra, E. Deprettere · 2002
The Jacobium is a dataflow processor intended for high-speed execution of a set of algorithms that are akin to the so-called Jacobi method for reducing a symmetric matrix to diagonal form using Givens rotations. The design of this processor has been undertaken as one of two cases in a recently proposed method for the quantitative analysis of domain-specific dataflow architectures. The method presupposes that the exploration of the processor's design space starts out of a given architecture template whose free parameters are to be determined in such a way that the ultimate specification is in some sense optimal for a set of applications that are given from the outset. Two templates have been considered in the Jacobium case: one for the complete (multiple processor element) processor and one for a typical processor element (PE). A parametrized VHDL version of the latter has been designed as well. The architecture of such a typical PE is presented here. It is equipped with a deep floating point Cordic pipeline, on-chip multiport memory to buffer operands and results, and several high-speed communication buses for communication between processing elements and the host. This parametrized architecture serves two purposes: it can provide realistic estimates for the PE parameters at the level of the complete processor; and it can be used to validate the exploration results.