Exact functional redundancy identification
Antonio Lioy, Massimo Poncino · 2002
Presents a functional method to identify redundancies in combinational logic circuits. It is based on the direct comparison of the good and faulty output functions, manipulated as binary decision diagrams (BDDs). Topological techniques are used to identify irredundant regions and hence to reduce the size of the circuit region whose Boolean function must be computed. Application to standard benchmarks shows the feasibility of the approach for real circuits.